1. Field of the Invention
The present invention generally relates to a method for testing large area integrated circuit chips and, more particularly, to utilizing a sacrificial metal level to create adequate size test pads and subsequently, after testing, removing the sacrificial metal level in a planarization step prior to the next metal level deposition.
2. Background Description
Manufacturing processes of large area integrated circuit (IC) chips tend to produce poor yields. This, in turn, increases the costs of the chips. It is therefore desirable to increase the yields of large area IC chips. Yields of large area IC chips could be improved by testing chip functionality prior to deposition of final metal levels. To achieve adequate test capability at such an intermediate level in the manufacturing process, sufficiently large pads must be available; however, such pads would normally interfere with subsequently deposited metal levels and vias.